CHIPS R&D Standardization Readiness Level Workshop

CHIPS R&D Standardization Readiness Level (StRL) Workshop

June 4-5, 2024

The CHIPS Research and Development Office’s Standardization Readiness Level (StRL) Workshop will be held as a hybrid virtual and in-person event at the Department of Commerce NIST campus in Boulder, CO from 9:00 a.m. to 5:00 p.m. Eastern Time June 4, 2024, and 9:00 am to 1:00 pm June 5, 2024.  This event will bring together technical experts from industry, academia, standards developing organizations, and industry alliances to consider community perspectives on metrics for standardization readiness.

Currently, StRL is a nascent conceptual framework that provides a structured approach to inform a standardization strategy for a given technology area through exploration of the elements of technology, metrology, market, and community. Considerations can include technology maturity, market community commitment and expressed need, the availability and willingness of an expert community to develop standards, the state of the requisite measurement science, the readiness of the user community to adopt standards if they existed, and the value proposition of the potential standard given the state of the market. NIST has been working with international standards working groups to define an StRL scale and apply it to other critical and emerging technology areas. This workshop will explore whether a well-defined StRL framework, tailored for use in semiconductor standards development, could serve as a crucial guide for determining if research outcomes should be integrated into voluntary industry standards activities.

This one and one-half day hybrid event provides an opportunity to network and exchange ideas with thought leaders across the sector. Both Day One and Day Two will feature plenary and panel sessions with renowned speakers, followed by interactive breakout sessions focusing on defining an StRL framework and its application to semiconductor-relevant technologies. Questions that will be considered include:

• What considerations would best inform the readiness of the technology, community, and market for embarking on a standards effort?
• Can a simple StRL framework with specific levels and criteria be established based on the technology, metrology, community, and market considerations? Is anything missing that should be considered?
• How can an overall StRL assessment of an opportunity for standards development be made based on the outcomes of the technology, metrology, community, and market considerations?
• How can the alignment between Technology Readiness Level (TRL), Manufacturing Readiness Level (MRL), and Standardization Readiness Level (StRL) be utilized to identify strategic standards opportunities, and how might this draw relevant TRL and MRL experts into the discussion?
• How can an StRL framework enhance communication and collaboration among researchers and SDOs?
• How can an StRL framework be integrated into the processes of SDOs?

The draft agenda is located on the “Agenda” tab and will be updated as the event nears. Key findings will be published in a post-workshop report and will inform standards planning efforts across the semiconductor innovation ecosystem and within the CHIPS R&D Office.

We encourage interested stakeholders, industry representatives, and standards developing organizations to participate actively in this pivotal event. We welcome both domestic and international participation, as fostering global collaboration and enriching the discussions on advancing semiconductor standards and innovation are paramount to success.

Join us at the CHIPS R&D Standardization Readiness Level (StRL) Workshop as we collaboratively shape the future of semiconductor and microelectronics standards, foster innovation, and advance the industry as a whole.