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CMOS Device and Reliability


The CMOS Device and Reliability Project develops advanced metrology tools to enable high performance CMOS (Complementary Metal Oxide Semiconductor) devices with sufficient reliability.

These tools are for the characterization of advanced transistors to understand the physics governing their performance and degradation. We deal with current problems as well as expected problems in the future. By working closely with semiconductor manufacturers, we deliver solutions that are important and timely.

Charles Cheung
A new ultra-sensitive magnetic resonance based defect spectroscopy for advanced CMOS device is under development.


Electron devices and their reliability have long been important topics of research at NIST. Over the years, we have always played a central role in this important field. Many of the commonly used test structures and test methodologies in the industry were developed at NIST. NIST also led many of the standard setting efforts.

Everything electronics, as we all have come to expect, get cheaper and better every year - a benefit of the relentless advance in CMOS technology. It is now a global business with over $300 billion in annual sales. The larger electronics industry that leverages the CMOS technology has annual sales of multi-trillion dollars. Electronics permeated every aspect of modern living and find its way into increasing more life critical functions. High performance electronics with high reliability provide the competitive advantage in modern market place.

The CMOS transistors currently in production are as small as 14 nm, and those in advanced development are smaller than 10 nm. Properly characterizing these devices and understanding factors that affect their performance and reliability are extremely challenging. Our work focus is on meeting these measurement challenges by pushing the known measurement technologies to the limit and developing new measurement capabilities. By emphasizing fundamental understanding of the measured phenomenon, we amplify our impact to the industry.

Major Accomplishments:

  • Developed a physical and quantitative model to link random telegraph noise (RTN) to specific device parameters – a major milestone in low-frequency noise physics.
  • Demonstrate a full circuit speed reliability assessment methodology for random logics.
  • Our series resistance extraction method was implemented at IMEC and SEMATECH. 

End Date:


Lead Organizational Unit:




Charles Cheung
301-975-3093 Telephone

100 Bureau Drive, M/S 8120
Gaithersburg, MD 20899-8120