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CMOS Device and Reliability



The CMOS Device and Reliability Project aims to develop new metrology tools for characterizing high-performance complementary metal-oxide-semiconductor (CMOS) materials and devices. The principle objective is to understand the underlying physics and atomic-scale defects responsible for critical failure and drift mechanisms that limit device performance and reliability. By working closely with semiconductor manufacturers, the project delivers timely metrology solutions and physical insight that are important for solving the most pressing development obstacles. Project scientists also stand ready to help U.S. manufacturers who use electronics to enhance product performance while achieving reliability targets as well as advancing product features to achieve a competitive advantage.

Charles Cheung

Figure 1. A new ultra-sensitive magnetic resonance based spectrometer, that enables unparalleled physical insight into atomic-scale defects, is currently under development.


Electronics are all around us and affect every aspect of modern society. Virtually any system, large or small, contains some type of electronics that may or may not be directly visible to the user. The key product differentiators are how well the device works (performance) and how long the device is usable (reliability).

While these electron devices and their reliability have long been important research areas at NIST, these technologies and the associated materials advance very quickly with older generations becoming obsolete in just a few years. Thus, there is an ever present need to develop and redefine new metrology tools and understand new physical phenomena to maximize performance and reliably in the newest technology generations. This requires a strong, fundamental understanding of the physics of electron device degradation, a solid understanding of what the measured data actually tells us, and a relentless pursuit of new and/or improved metrology tools.

The CMOS Device and Reliability Project strives to be at the forefront of both electron device reliability physics and reliability metrology. Some of the recent and ongoing activities include:

  • Development of a highly sensitive electron spin resonance technique that provides un-paralleled access to the chemical and physical nature of atomic scale defects that limit device performance and reliability. The technique is also particularly amenable to soft matter studies of naturally occurring free radicals or purposely labeled biomolecular structures.
  • Circuit speed (≥ GHz) reliability metrology that enables individual device level reliability to be evaluated in a highly realistic "circuit" environment. Allows one to determine the impact of device degradation on the critical timing of random logic circuitry.
  • Massively parallel device level reliability characterization system that enables the simultaneous testing of several thousand devices. Delivers previously unattainable failure statistics that are increasingly necessary for advance device development.
  • Development and refinement of the ubiquitous "charge pumping" measurement concept. Continuously adapting the metrology methods to suit modern needs while developing an improved physics-based understanding.
  • Development of high speed characterization metrology to study resistive random access memory (RRAM) devices. Understanding the fast forming transients which determine the switching characteristics are critical to commercializing this promising memory technology.

Major Accomplishments:


  • Demonstrated a >20,000X improvement in sensitivity compared to the best commercially available electron spin resonance spectrometer.
  • Observed and modeled self-interference of coherent electrons in nano-scale devices and developed a new understanding of electron injection in advanced CMOS devices.
  • Successfully applied transition-state theory to the charge-capture process and explained the origin of wildly scattered values of reported defect capture cross sections.


  • Developed a method to determine the impact of transistor degradation to critical timing of random logic circuit.
  • First demonstration of the massively parallel long-term reliability test system.
  • Established the relationship between dissipated energy and filament formation in next generation resistive random access memory (RRAM) technology.


  • Demonstrated frequency modulated charge pumping which enables quantitative defect measurements in ultra-scaled devices with high gate leakage current.
  • Developed the first ultra-fast resistive random access memory switching measurement capability.
  • Developed accurate fast capacitance-voltage measurement.
High-speed amplified probe
Figure 2. High speed amplifier wafer probe tip developed by the CMOS Device and Reliability project.

End Date:


Lead Organizational Unit:




Facilities/Tools Used:

  • A cryo probe station with 2 Tesla magnetic field and dual scan probe will be delivered this fall.
  • A custom built room temperature continuous wave near-field non-resonant high-definition electron spin resonance spectrometer
  • A massively parallel wafer-level long-term reliability test system.
  • Various microwave equipment up to 100 GHz.
  • Numerous wafer probe stations and supporting equipment (oscilloscopes, pulse generators, etc.)
  • NIST Nanofab


Kin (Charles) P. Cheung, Project Leader
Jason Campbell
Jason Ryan
Dmitry Veksler


Pragya Shrestha
Jihong Kim
Zakariae Chbili
David Nminibapiel
Vasileia Georgiou
Jaafar Chbili


Charles Cheung
301-975-3093 Telephone

100 Bureau Drive, M/S 8120
Gaithersburg, MD 20899-8120