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Dr. John S. Suehle

Dr. Suehle is the leader of and a supervisory electrical engineer in the CMOS Reliability and Advanced Devices Group (683.06) in the Semiconductor & Dimensional Metrology Division (683) of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology (NIST). He received his B.S., M.S., and Ph.D. degrees in electrical engineering from the University of Maryland, College Park, in 1980, 1982, and 1988, respectively. In 1981, he received a Graduate Research Fellowship with the National Institute of Standards and Technology (NIST), Gaithersburg, MD. Since 1982, he has been working in the Semiconductor Electronics Division at NIST, where he is leader of the CMOS and Novel Devices Group.

Dr. Suehle's research activities include failure and wear-out mechanisms of semiconductor devices, radiation effects on microelectronic devices, micro-electro-mechanical-systems (MEMS), and molecular electronic devices. Dr. Suehle has published over 100 technical papers or conference proceedings and holds 5 U.S. patents.

Dr. Suehle serves as the chairman of the Oxide Integrity Working Group of the EIA/JEDEC JC 14.2 Standards Committee responsible for wafer-level reliability. His is a Fellow of the IEEE.

Dr. John S. Suehle


Leader, Supervisory Electrical Engineer
Semiconductor & Dimensional Metrology Division
CMOS Reliability and Advanced Devices Group

Employment History:

  • 1982-present: National Institute of Standards and Technology, Gaithersburg MD.
  • 1980-1982: University of Maryland/NIST Graduate Fellowship, University of Maryland, College Park MD.


  • Ph.D., Electrical Engineering, University of Maryland, 1988.
    • Dissertation: Characterization and Modeling of Localized Hot-Carrier- Induced Charge Effects in
      Microelectronic Switching Circuits.
  • MSEE, Thesis Option, University of Maryland, 1982.
    • Thesis: An Experimental Study of Wafer Level Acceptance Testing Based on Sampling Test Chip Data.
  • BSEE, University of Maryland, 1980.

Phone: 301-975-2247