Sample behavioral waveforms for design file altpll0.v

The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design altpll0.v. The design altpll0.v has Cyclone II FAST pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 13157 ps. CLK0 multiply by = 2, CLK0 divide by = 1, CLK0 phase_shift = 0 Output port LOCKED is used. This port will go high when the PLL locks to the input clock.