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Search Publications by: Advait Madhavan (Assoc)

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Displaying 1 - 18 of 18

Measurement-driven neural-network training for integrated magnetic tunnel junction arrays

May 14, 2024
Author(s)
William Borders, Advait Madhavan, Matthew Daniels, Vasileia Georgiou, Martin Lueker-Boden, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland, Brian Hoskins
The increasing scale of neural networks needed to support more complex applications has led to an increasing requirement for area- and energy-efficient hardware. One route to meeting the budget for these applications is to circumvent the von Neumann

Measurement-driven Langevin modeling of superparamagnetic tunnel junctions

March 19, 2024
Author(s)
Liam Pocher, Temitayo Adeyeye, Sidra Gibeault, Philippe Talatchian, Ursula Ebels, Daniel Lathrop, Jabez J. McClelland, Mark Stiles, Advait Madhavan, Matthew Daniels
Superparamagnetic tunnel junctions are important devices for a range of emerging technologies, but most existing compact models capture only their mean switching rates. Capturing qualitatively accurate analog dynamics of these devices will be important as

Neural networks three ways: unlocking novel computing schemes using magnetic tunnel junction stochasticity

September 28, 2023
Author(s)
Matthew Daniels, William Borders, Nitin Prasad, Advait Madhavan, Sidra Gibeault, Temitayo Adeyeye, Liam Pocher, Lei Wan, Michael Tran, Jordan Katine, Daniel Lathrop, Brian Hoskins, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland
Due to their interesting physical properties, myriad operational regimes, small size, and industrial fabrication maturity, magnetic tunnel junctions are uniquely suited for unlocking novel computing schemes for in-hardware neuromorphic computing. In this

Magnetic tunnel junction-based crossbars: improving neural network performance by reducing the impact of non-idealities

July 13, 2023
Author(s)
William Borders, Nitin Prasad, Brian Hoskins, Advait Madhavan, Matthew Daniels, Vasileia Gerogiou, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland
Increasingly higher demand in chip area and power consumption for more sophisticated artificial neural networks has catalyzed efforts to develop architectures, circuits, and devices that perform like the human brain. However, many novel device technologies

Characterization of Noise in CMOS Ring Oscillators at Cryogenic Temperatures

July 12, 2023
Author(s)
Prashansa Mukim, Pragya Shrestha, Advait Madhavan, Nitin Prasad, Jason Campbell, Forrest Brewer, Mark Stiles, Jabez J. McClelland
Allan deviation provides a means to characterize the time-dependence of noise in oscillators and potentially identify the source characteristics. Measurements on a 130nm, 7-stage ring oscillator show that the Allan deviation declines from 300K to 150K as

Ultrafast ID-VG Technique for Reliable Cryogenic Device Characterization

March 21, 2023
Author(s)
Pragya Shrestha, Akin Akturk, Brian Hoskins, Advait Madhavan, Jason Campbell
An in-depth understanding of the transient operation of devices at cryogenic temperatures remains experimentally elusive. However, the impact of these transients has recently become important in efforts to develop both electronics to support quantum

Implementation of a Binary Neural Network on a Passive Array of Magnetic Tunnel Junctions

July 18, 2022
Author(s)
Jonathan Goodwill, Nitin Prasad, Brian Hoskins, Matthew Daniels, Advait Madhavan, Lei Wan, Tiffany Santos, Michael Tran, Jordan Katine, Patrick Braganca, Mark Stiles, Jabez J. McClelland
The increasing scale of neural networks and their growing application space have produced a demand for more energy and memory efficient artificial-intelligence-specific hardware. Avenues to mitigate the main issue, the von Neumann bottleneck, include in

Mutual control of stochastic switching for two electrically coupled superparamagnetic tunnel junctions

August 19, 2021
Author(s)
Philippe Talatchian, Matthew Daniels, Advait Madhavan, Matthew Pufall, Emilie Jue, William Rippard, Jabez J. McClelland, Mark Stiles
Superparamagnetic tunnel junctions (SMTJs) are promising sources for the randomness required by some compact and energy-efficient computing schemes. Coupling them gives rise to collective behavior that could be useful for cognitive computing. We use a

Impact ionization-induced bistability in CMOS transistors at cryogenic temperatures for capacitorless memory applications

July 29, 2021
Author(s)
Alexander Zaslavsky, Curt A. Richter, Pragya Shrestha, Brian Hoskins, Son Le, Advait Madhavan, Jabez J. McClelland
Cryogenic operation of complementary metal oxide semiconductor (CMOS) silicon transistors is crucial for quantum information science, but it brings deviations from standard transistor operation. Here we report on sharp current jumps and stable hysteretic

A System for Validating Resistive Neural Network Prototypes

July 27, 2021
Author(s)
Brian Hoskins, Mitchell Fream, Matthew Daniels, Jonathan Goodwill, Advait Madhavan, Jabez J. McClelland, Osama Yousuf, Gina C. Adam, Wen Ma, Muqing Liu, Rasmus Madsen, Martin Lueker-Boden
Building prototypes of heterogeneous hardware systems based on emerging electronic, magnetic, and photonic devices is an increasingly important area of research. On the face of it, the novel implementation of these systems, especially for online learning

Temporal Memory with Magnetic Racetracks

December 1, 2020
Author(s)
Hamed Vakili, Mohammed N. Sakib, Samiran Ganguly, Mircea Stan, Matthew Daniels, Advait Madhavan, Mark D. Stiles, Avik W. Ghosh
Race logic is a relative timing code that represents information in a wavefront of digital edges on a set of wires in order to accelerate dynamic programming and machine learning algorithms. Skyrmions, bubbles, and domain walls are mobile magnetic

Storing and retrieving wavefronts with resistive temporal memory

October 10, 2020
Author(s)
Advait Madhavan, Mark D. Stiles
We extend the reach of temporal computing schemes by developing a memory for multi-channel temporal patterns or "wavefronts." This temporal memory re-purposes conventional one-transistor-one-resistor (1T1R) memristor crossbars for use in an arrival-time

Energy-efficient stochastic computing with superparamagnetic tunnel junctions

March 5, 2020
Author(s)
Matthew W. Daniels, Advait Madhavan, Philippe Talatchian, Alice Mizrahi, Mark D. Stiles
Stochastic computing has been limited by the inaccuracies introduced by correlations between the pseudorandom bitstreams used in the calculation. We hybridize a stochastic version of magnetic tunnel junctions with basic CMOS logic gates to create a

Streaming Batch Eigenupdates for Hardware Neural Networks

August 6, 2019
Author(s)
Brian D. Hoskins, Matthew W. Daniels, Siyuan Huang, Advait Madhavan, Gina C. Adam, Nikolai B. Zhitenev, Jabez J. McClelland, Mark D. Stiles
Neuromorphic networks based on nanodevices, such as metal oxide memristors, phase change memories, and flash memory cells, have generated considerable interest for their increased energy efficiency and density in comparison to graphics processing units

A Truth-Matrix View into Unary Computing

June 22, 2019
Author(s)
Advait Madhavan, Georgios Tzimpragos, Mark D. Stiles, Timothy Sherwood
Our community has been exploring Time-of-arrival based codes as a candidate for very low energy information processing. A ``space-time'' algebra has been recently proposed that captures the essential features of such a paradigm. In order to gain some