Silicon Nanowire NVM Cell Using High-k Dielectric Charge Storage Layer

Published

December 5, 2008

Author(s)

Xiaoxiao Zhu, Yang Yang, Qiliang Li, D. E. Ioannou, John S. Suehle, Curt A. Richter

Abstract

Si nanowire (SiNW) channel non-volatile memory (NVM) cells were fabricated by a 'self-alignment' process. First, a layer of thermal SiO2 was grown on a silicon wafer by dry oxidation, and the SiNWs were then grown by chemical vapor deposition in pre-defined locations. This was followed by depositing the gate dielectric, which almost surrounds the nanowire and consists of three stacked layers: SiO2 blocking layer, HfO2 charge-storing layer and a thin tunneling oxide layer. Source/drain and gate electrodes were formed by photolithography and lift-off, and the devices were electrically tested. As expected from this fabrication process and the enhanced electrostatic control of the 'surrounding' gate, excellent cell characteristics were obtained.

Citation

Microelectronic Engineering

Volume

85

Pub Type

Journals

Download Paper

Local Download

Keywords

Nanoelectronics, Silicon nanowire, Self-alignment, Non-volatile memory, Hafnium oxide

Citation

Zhu, X. , Yang, Y. , Li, Q. , Ioannou, D. , Suehle, J. and Richter, C. (2008), Silicon Nanowire NVM Cell Using High-k Dielectric Charge Storage Layer, Microelectronic Engineering, [online], https://tsapps.nist.gov/publication/get_pdf.cfm?pub_id=33041 (Accessed December 26, 2024)