May 13, 2001
Author(s)
John S. Suehle, Eric M. Vogel, Monica D. Edelstein, Curt A. Richter, Nhan Van Nguyen, Igor Levin, Debra Kaiser, Hanchang F. Wu, J B. Bernstein
As the feature sizes of complementary metal-oxide-semiconductor (CMOS) devices are scaled downward, the gate dielectric thickness must also decrease to maintain a value of capacitance to reduce short-channel effects and to keep device drive current at an