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Search Publications by: Jason Campbell (Fed)

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Displaying 26 - 50 of 229

An Ultra-fast Multi-level MoTe2-based RRAM

January 17, 2019
Author(s)
Albert Davydov, Leonid A. Bendersky, Sergiy Krylyuk, Huairuo Zhang, Feng Zhang, Joerg Appenzeller, Pragya R. Shrestha, Kin P. Cheung, Jason P. Campbell
We report multi-level MoTe2-based resistive random-access memory (RRAM) devices with switching speeds of less than 5 ns due to an electric-field induced 2H to 2Hd phase transition. Different from conventional RRAM devices based on ionic migration, the

Slow- and rapid-scan frequency-swept electrically detected magnetic resonance of MOSFETs with a non-resonant microwave probe within a semiconductor wafer-probing station

January 14, 2019
Author(s)
Duane J. McCrory, Mark Anders, Jason Ryan, Pragya Shrestha, Kin P. Cheung, Patrick M. Lenahan, Jason Campbell
We report on a novel electron paramagnetic resonance (EPR) technique that merges electrically detected magnetic resonance (EDMR) with a conventional semiconductor wafer probing station. This union, which we refer to as wafer-level EDMR (WL-EDMR), allows

Parasitic engineering for RRAM control

October 15, 2018
Author(s)
Pragya R. Shrestha, David M. Nminibapiel, Dmitry Veksler, Jason P. Campbell, Jason T. Ryan, helmut Baumgart, Kin P. Cheung
The inevitable current overshoot which follows forming or switching of filamentary resistive random access memory (RRAM) devices is often perceived as a source of variability that should be minimized. This sentiment has resulted in efforts to curtail the

Non-tunneling origin of the 1/f noise in SiC MOSFET

July 1, 2018
Author(s)
Kin (Charles) Cheung, Jason Campbell
Abstract: It has long been established that MOSFET random telegraph noise and the cumulative 1/f noise is the result of inversion charge tunneling in and out of bulk traps in the gate oxide near the interface. The tunneling nature is a key concept upon

First Direct Experimental Studies of Hf0.5Zr0.5O2 Ferroelectric Polarization Switching Down to 100-picosecond in Sub-60mV/dec Germanium Ferroelectric Nanowire FETs

June 18, 2018
Author(s)
Wonil Chung, Mengwei Si, Pragya Shrestha, Jason Campbell, Kin P. Cheung, Peide Ye
In this work, ultrafast pulses with pulse widths ranging from 100 ps to seconds were applied on the gate of Ge ferroelectric (FE) nanowire (NW) pFETs with FE Hf0.5Zr0.5O2 (HZO) gate dielectric exhibiting steep subthreshold slope (SS) below 60 mV/dec bi

Glassy-Electret Random Access Memory - A naturally Nanoscale Memory Concept

April 19, 2018
Author(s)
Jason Campbell, Pragya Shrestha, Vasileia Georgiou, D. E. Ioannou, Kin (Charles) Cheung
Self-heating is a serious issue in state-of-the-art MOSFET technology. Much efforts are currently being made to combat this problem to enable further scaling. In this work, self-heating in nanoscale MOSFET is leveraged and enhanced to enable a new memory

Wafer-Level Electrically Detected Magnetic Resonance:Magnetic Resonance in a Probing Station

March 20, 2018
Author(s)
Duane J. McCrory, Mark Anders, Jason Ryan, Pragya Shrestha, Kin P. Cheung, Patrick M. Lenahan, Jason Campbell
We report on a novel semiconductor reliability technique that incorporates an electrically detected magnetic resonance (EDMR) spectrometer within a conventional semiconductor wafer probing station. EDMR is an ultrasensitive electron paramagnetic resonance

Analysis and Control of RRAM Overshoot Current

January 15, 2018
Author(s)
Pragya R. Shrestha, David M. Nminibapiel, Jason P. Campbell, Jason T. Ryan, Dmitry Veksler, Helmut Baumgart, Kin P. Cheung
To combat the large variability problem in RRAM,current compliance elements are commonly used to limit the inrush current during the forming operation. Regardless of the compliance implementation (1R-1R or 1T-1R), some degree of current overshoot is

Ferroelectricity in Polar Polymer-based FETs: A Hysteresis Analysis

January 15, 2018
Author(s)
Vasileia Georgiou, Dmitry Veksler, Jason Campbell, Jason Ryan, Pragya Shrestha, D. E. Ioannou, Kin P. Cheung
There is an increasing number of reports on polar polymer-based Ferroelectric Field Effect Transistors (FeFETs), where the hysteresis of the drain current - gate voltage (Id-Vg) curve is investigated as the result of the ferroelectric polarization effect

Highly Efficient Rapid Annealing of Thin Polar Polymer Film Ferroelectric Devices at Sub-Glass Transition Temperature

December 18, 2017
Author(s)
Vasileia Georgiou, Dmitry Veksler, Jason T. Ryan, Jason P. Campbell, Pragya R. Shrestha, D. E. Ioannou, Kin P. Cheung
An unexpected rapid anneal of electrically active defects in an ultra-thin (15.5 nm) polar polyimide film at and below glass transition temperature (Tg) is reported. The polar polymer is the gate dielectric of a thin-film-transistor (TFT). Gate leakage