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Displaying 401 - 425 of 718

INTER-LABORATORY COMPARISON OF NOISE-PARAMETER MEASUREMENTS ON CMOS DEVICES WITH 0.12 um GATE LENGTH

December 1, 2005
Author(s)
James P. Randa, Susan L. Sweeney, Tom McKay, Dave K. Walker, David R. Greenberg, Jon Tao, Judah Mendez, G. Ali Rezvani, John J. Pekarik
We present results of an interlaboratory comparison of S-parameter and noise-parameter measurements performed on 0.12 υm gate-length CMOS transistors. Copies of the same device were measured at three different laboratories (IBM, NIST, RFMD), and the

Comparison of Gains Determined from the Extrapolation and Pattern Integration Methods

October 30, 2005
Author(s)
Michael H. Francis, Katherine MacReynolds, Jeffrey R. Guerrieri
Scientists at the National Institute of Standards (NIST) have measured the gain of several antennas using two different methods. The first method is the three-antenna extrapolation method developed at NIST in the early 1970s. The second method is the

Characterization of Normally-off SiC Vertical JFET Devices and Inverter Circuits

October 1, 2005
Author(s)
Jih-Sheng Lai, H. Yu, J. Zhang, Y. Li, Kuang Sheng, J.H. Zhao, Allen R. Hefner Jr.
A normally-off SiC JFETs has been characterized under static and dynamic operating conditions. Two application oriented inverter circuits were constructed for additional tests under soft- and hard-switching conditions. The single-phase soft-switching

Electrical Methods for Mechanical Characterization of Interconnect Thin Films

September 1, 2005
Author(s)
Robert Keller, Cynthia A. Volkert, Roy H. Geiss, Andrew Slifka, David T. Read, Nicholas Barbosa, Reiner Monig
We describe the use of electrical methods for evaluating mechanical reliability and properties of patterned copper and aluminum interconnects on silicon substrates. The approach makes use of controlled Joule heating, which causes thermal strains in the

GerberTranslator: Moving towards new PCB standards

August 29, 2005
Author(s)
Matthew L. Aronoff, John V. Messina
This paper describes the key features of the NIST-developed software tool called ?GerberTranslator?. GerberTranslator is a software translator which automates the majority of the work in converting a printed circuit board (PCB) described in the industry

Uncertainties in Spherical Near-Field Antenna Measurements

August 3, 2005
Author(s)
Michael H. Francis, Ronald C. Wittmann, Jin-Seob Kang
A general approach is presented for estimating uncertainties in far-field parameters obtained from spherical near-field antenna measurements. The error is approximately bounded in terms of the uncertainty of the probe's receiving pattern and the

Workshop on Reliability Issues in Nanomaterials

August 1, 2005
Author(s)
Robert Keller, David T. Read, Roop L. Mahajan
The Workshop on Reliability Issues in Nanomaterials was held at the Boulder Laboratories of the National Institute of Standards and Technology (NIST) on August 17-19, 2004. It was designed to promote a particular subset of NIST?s responsibilities under the

A current-density scale for characterizing nonlinearity in high-Tc superconductors

June 1, 2005
Author(s)
Kenneth Leong, James C. Booth, Susan A. Schima
In this paper, we characterize microwave nonlinearity in a high temperature superconducting (HTS) thin film sample by measurement of a geometry-independent current-density scale j o. This quanity j specifies the strenth of a material-dependent nonlinearity

Metrology for High-Voltage, High-Speed Silicon-Carbide Power Devices

April 4, 2005
Author(s)
Allen R. Hefner Jr., David W. Berning, Colleen E. Hood
Performance metrics and test instrumentation needs for emerging high-voltage, high-speed SiC power devices are described. Unique power device and package thermal measurement test systems and parameter extraction methods are introduced, and applied to

The OATS Method Revisited

April 1, 2005
Author(s)
Christopher L. Holloway, Perry F. Wilson, Robert German
Open area test sites (OATS) or equivalent semi-anechoic chambers are the most commonly used sites for EMC emissions tests. This article discusses the origins of this test methodology and revisits the interference problem (broadcast media) that the OATS

Electric Current Induced Thermomechanical Fatigue Testing of Interconnects

March 1, 2005
Author(s)
Robert Keller, Roy H. Geiss, Yi-Wen Cheng, David T. Read
We demonstrate the use of electrical methods for evaluating the thermomechanical fatigue properties of patterned aluminum and copper interconnects on silicon-based substrates. Through a careful selection of alternating current frequency and current density

Microstructure Evolution during Alternating-Current-lnduced Fatigue

November 1, 2004
Author(s)
Robert Keller, Roy H. Geiss, Yi-Wen Cheng, David T. Read
Subjecting electronic interconnect lines to high-density, low.frequency alternating current creates cyclic thermomechanical stresses that eventually cause electrical failure. A detailed understanding of the failure process could contribute to both

Multiport Investigation of the Coupling of High-Impedance Probes

November 1, 2004
Author(s)
Dylan F. Williams, Pavel Kabos, Uwe Arz
We used an on-wafer measurement technique that combines two- and three-port frequency-domain mismatch corrections in order to characterize the influence of a high-impedance probe on a device under test. The procedure quantifies the probe’s load of the

Spin transfer switching of spin valve nanopillars using nanosecond pulsed currents

October 29, 2004
Author(s)
Shehzaad F. Kaka, Matthew Pufall, William Rippard, Thomas J. Silva, Stephen E. Russek, Jordan A. Katine, Matt Carey
Spin valve nanopillars are reversed via the mechanism of spin momentum transfer using current pulses applied perpendicular to the film plane of the device. The applied pulses were varied in amplitude from 1.8 to 7.8 mA, and varied in duration within the

Electrostatic Discharge Protection For Embedded-Sensor Systems-On-a-Chip

October 8, 2004
Author(s)
Javier A. Salcedo, Juin J. Liou, Muhammad Afridi, Allen R. Hefner Jr., Ankush Varma
The robustness of Embedded-Sensor (ES) System-on-a-Chip (SoC) applications involves several design constrains that require a unique assessment. For example, space-efficient electrostatic discharge protection (ESD) must be provided to protect the CMOS

Compact Models for Silicon Carbide Power Devices

October 1, 2004
Author(s)
Ty R. McNutt, Allen R. Hefner Jr., Alan Mantooth, David W. Berning, Ranbir Singh
The development of compact silicon carbide (SiC) power semiconductor device models for circuit simulation is described. The work detailed herein has been used to model power Schottky, Merged-PiN-Schottky, PiN diode, and MOSFET models. In these models, the
Displaying 401 - 425 of 718