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Displaying 1 - 25 of 738

A 4-mW 2.2-6.9 GHz LNA in 16nm FinFET Technology for Cryogenic Applications

December 9, 2024
Author(s)
Runzhou Chen, Hamdi Mani, Phil Marsh, Richard Al Hadi, Pragya Shrestha, Jason Campbell, Christopher Chen, Hao-Yu Chen, Kosmas Galatsis, Mau-Chung Frank Chang
This work presents the design and measurement of a low-power wide-band cryogenic low-noise amplifier (LNA) that operates in a wide temperature range using 16nm FinFET technology. The LNA is packaged and measured at both room and cryogenic temperatures. It

On-chip synthesis of quasi two-dimensional semimetals from multi-layer chalcogenides

September 23, 2024
Author(s)
Jun Cai, Huairuo Zhang, Yuanqiu Tan, Zheng Sun, Rahul Tripathi, Peng Wu, Sergiy Krylyuk, Caleb Suhy, Jing Kong, Albert Davydov, Zhihong Chen, Joerg Appenzeller
Reducing the dimensions of materials from three to two, or quasi-two, provides a fertile platform for exploring emergent quantum phenomena and developing next-generation electronic devices. However, growing high-quality, ultrathin, quasi two-dimensional

On-Wafer Calibration Comparisons of Multiline TRL with Platinum and Gold Conductors

July 30, 2024
Author(s)
Tomasz Karpisz, Jacob Pawlik, Johannes Hoffmann, Sarah Evans, Christian Long, Nathan Orloff, James Booth, Angela Stelson
On-wafer calibrations are critical for measurements of embedded devices at the correct reference planes. A major challenge in on-wafer calibrations is the development of accurate calibrations that cover a frequency range from MHz to THz. Another challenge

On-Wafer Capacitor Characterization Including Uncertainty Estimates Up to 1.0 THz

July 19, 2024
Author(s)
Robert Jones, Jerome Cheron, Benjamin Jamroz, Dylan Williams, Ari Feldman, Peter Aaen, Christian Long, Nathan Orloff
In this article we extract the capacitance of shunt and series metal-insulator-metal capacitors from on-wafer S-parameter measurements in the WR1.0 waveguide band. We verify consistency of the measured devices in two different state-of-the-art terahertz

Fully integrated multifunctional sensor and open-source ASIC for flexible wearables

June 25, 2024
Author(s)
Anhang Li, Hongyi Wu, Ashbir Aviat Fadila, Chanho Kye, Arvind Balijepalli, Johan Euphrosine, Tim Ansell, Nigel Coburn, Sachin Nadig, Mehdi Saligane
The open-source hardware movement has made significant progress over the past few years. Increasingly, more individuals are engaging with and participating in the open-source chip design community - not only to design their own chips with the available

Instrument Development for Spectroscopic Ellipsometry and Diffractometry in the EUV

April 24, 2024
Author(s)
Stephanie Moffitt, Bryan Barnes, Thomas A. Germer, Steven Grantham, Eric Shirley, Martin Sohn, Daniel Sunday, Charles S. Tarrio
Semiconductor devices are noted for ever-decreasing dimensions but now are also becoming more complex. While scanning probe microscopy can still resolve the smallest features, it does not have the throughput for high-volume characterization of full wafers

Threshold and Laser Conversion in Nanostructured-Resonator Parametric Oscillators

January 10, 2024
Author(s)
Haixin Liu, Grant Brodnik, Jizhao Zang, David Carlson, Jennifer Black, Scott Papp
We explore optical parametric oscillation (OPO) in nanophotonic resonators, enabling arbitrary, nonlinear phase matching and nearly lossless control of energy conversion. Such pristine OPO laser converters are determined by nonlinear light-matter

A Fully Integrated, Automatically Generated DC-DC Converter Maintaining > 75% Efficiency From 398 K Down to 23 K Across Wide Load Ranges in 12-nm FinFET

January 1, 2024
Author(s)
Anhang Li, Jeongsup Lee, Prashansa Mukim, Brian Hoskins, Pragya Shrestha, David Wentzloff, David Blaauw, Dennis Sylvester, Mehdi Saligane
This paper presents a fully integrated recursive successive-approximation switched capacitor (RSC) DC-DC converter implemented using an automatic cell-based layout generation in 12 nm FinFET technology. A novel design methodology is demonstrated based on

Experimental demonstration of a robust training method for strongly defective neuromorphic hardware

December 11, 2023
Author(s)
William Borders, Advait Madhavan, Matthew Daniels, Vasileia Georgiou, Martin Lueker-Boden, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland, Brian Hoskins
Neural networks are increasing in scale and sophistication, catalyzing the need for efficient hardware. An inevitability when transferring neural networks to hardware is that non-idealities impact performance. Hardware-aware training, where non-idealities

Microstrip and Grounded CPW Calibration Kit Comparison for On-Wafer Transistor Characterization from 220 GHz to 325 GHz

November 15, 2023
Author(s)
Rob Jones, Jerome Cheron, Bryan Bosworth, Ben Jamroz, Dylan Williams, Miguel Urteaga, Ari Feldman, Peter Aaen
In this paper, we investigate the effect of two calibration errors, probe placement and capacitance per unit length, on transistor characterization from 220 GHz to 325 GHz on both a microstrip and an inverted coplanar waveguide with a via stitched ground

EDFAS FA TECHNOLOGY ROADMAP DIE-LEVEL ROADMAP COUNCIL (DLRC) POST-ISOLATION DOMAIN TECHNICAL REPORT - JAN 2023

November 10, 2023
Author(s)
Vinod Narang, Zhang Chuan, David Su, Phil Kaszuba, Steven Herschbein, Alan Street, Eckhard Langer, Martin von Haartman, Yu Zhu, Baohua Niu, Erwin Hendarto, Bryan Tracy, Jochonia Nxumalo, Rik Otte, Keana C. K. Scott
Semiconductor technologies are advancing at a rapid pace, with ongoing developments in logic and memory scaling, the introduction of new materials and transistor architectures, and the integration of advanced packaging heterogeneous technologies such as

Magnetic tunnel junction-based crossbars: improving neural network performance by reducing the impact of non-idealities

July 13, 2023
Author(s)
William Borders, Nitin Prasad, Brian Hoskins, Advait Madhavan, Matthew Daniels, Vasileia Gerogiou, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland
Increasingly higher demand in chip area and power consumption for more sophisticated artificial neural networks has catalyzed efforts to develop architectures, circuits, and devices that perform like the human brain. However, many novel device technologies

Characterization of Noise in CMOS Ring Oscillators at Cryogenic Temperatures

July 12, 2023
Author(s)
Prashansa Mukim, Pragya Shrestha, Advait Madhavan, Nitin Prasad, Jason Campbell, Forrest Brewer, Mark Stiles, Jabez J. McClelland
Allan deviation provides a means to characterize the time-dependence of noise in oscillators and potentially identify the source characteristics. Measurements on a 130nm, 7-stage ring oscillator show that the Allan deviation declines from 300K to 150K as

Measurement and Gate-Voltage Dependence of Channel and Series Resistances in Lateral Depletion-Mode b-Ga2O3 MOSFETs

June 9, 2023
Author(s)
Ory Maimon, Neil Moser, Kyle Liddy, Andrew Green, Kelson Chabak, Kin (Charles) Cheung, Sujitra Pookpanratana, Qiliang Li
Lateral depletion-mode, beta-phase gallium oxide (β-Ga2O3) metal-oxide-semiconductor field-effect transistors (MOSFETs) with source-drain spacings of 3 µm, 8 µm, and 13 µm are studied using a modified Transfer Length Method (TLM) to obtain sheet

V-Ramp test and gate oxide screening under the "lucky" defect model

May 15, 2023
Author(s)
Kin (Charles) Cheung
The persistent (after exhaustive wafer cleaning) extrinsic breakdown distribution of thick gate oxides requires early breakdown mechanisms beyond the popular local thinning model to explain. The success of the 'Lucky" defect model in fulfilling this role
Displaying 1 - 25 of 738