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Search Publications by: Richard A. Allen (Fed)

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Displaying 26 - 50 of 269

Metrology Needs for TSV Fabrication

March 4, 2014
Author(s)
Victor H. Vartanian, Richard A. Allen, Larry Smith, Klaus Hummler, Steve Olson, Brian Sapp
This paper focuses on the metrology needs and challenges of through silicon via (TSV) fabrication, consisting of TSV etch, liner, barrier, and seed (L/B/S) depositions, copper plating, and copper CMP. These TSVs, with typical dimensions within a factor of

Detection of 3D Interconnect Bonding Voids by IR Microscopy

February 20, 2014
Author(s)
Jonny H?glund, Zoltan Kiss, Gyorgy Nadudvari , Zsolt Kovacs, Szabolcs Velkei, Moore Chris, Victor H. Vartanian, Richard A. Allen
There are a number of factors driving 3D integration including reduced power consumption, RC delay, and form factor as well as increased bandwidth. However, before these advantages can be realized, various technical and cost hurdles must be overcome. One

TSV Reveal height and bump dimension metrology by the TSOM method

April 30, 2013
Author(s)
Ravikiran Attota, Haesung Park, Victor H. Vartanian, Ndubuisi G. Orji, Richard A. Allen
Through-focus scanning optical microscopy (TSOM) transforms conventional optical microscopes into truly 3D metrology tools for nanoscale- to- microscale dimensional analysis with nanometer-scale sensitivity. Although not a resolution enhancement method

The MEMS 5-in-1 Test Chips (Reference Materials 8096 and 8097)

March 27, 2013
Author(s)
Janet M. Cassard, Jon C. Geist, Craig D. McGray, Richard A. Allen, Muhammad Y. Afridi, Brian J. Nablo, Michael Gaitan, David G. Seiler
This paper presents an overview of the Microelectromechanical Systems (MEMS) 5-in-1 Reference Material (RM), which is a single test chip with test structures from which material and dimensional properties are obtained using five documentary standard test

EVALUATING METHODS OF SHIPPING THIN SILICON WAFERS FOR 3D STACKED APPLICATIONS

November 7, 2012
Author(s)
Richard A. Allen, Urmi Ray, Vidhya Ramachandran, Iqbal Ali, David T. Read, Andreas Fehk?hrer, J?rgen Burggraf
An experiment was performed to develop a method for choosing appropriate packaging for shipping 300 mm silicon wafers thinned to 100 µm or less for three-dimensional stacked integrated circuits (3DS-ICs). 3DS-ICs hold the promise of improved performance

Robust Auto-Alignment Technique for Orientation-Dependent Etching of Nanostructures

May 29, 2012
Author(s)
Craig D. McGray, Richard J. Kasica, Ndubuisi G. Orji, Ronald G. Dixson, Michael W. Cresswell, Richard A. Allen, Jon C. Geist
A robust technique is presented for auto-aligning nanostructures to slow-etching crystallographic planes in materials with diamond cubic structure. Lithographic mask patterns are modified from the intended dimensions of the nanostructures to compensate for

Rectangular Scale-Similar Etch Pits in Monocrystalline Diamond

September 15, 2011
Author(s)
Craig D. McGray, Richard A. Allen, Marc J. Cangemi, Jon C. Geist
Etching of monocrystalline diamond in oxygen and water vapor at 1100° C through small pores in a silicon nitride film produced smooth-walled rectangular cavities. The cavities were imaged by electron microscope and measured by interferometric microscopy

Test Structure Fundamentals

April 4, 2011
Author(s)
Richard A. Allen
Test structures are critical tools for semiconductor manufacturers, allowing for understanding of the process and individual circuit elements that cannot be acquired from measurements of the circuits, which can have billions of transistors and other

Intercomparison of Methods for Detecting and Characterizing Voids in Bonded Wafer Pairs

October 1, 2010
Author(s)
Richard A. Allen, Andrew C. Rudack, David T. Read, Winthrop A. Baylies
The Wafer Bond Task Force of the SEMI MEMS Standards Committee has begun a round robin experiment to evaluate methods for identifying and characterizing voids in bonded wafer pairs for three-dimensional integrated circuit (3D IC) applications. Due to the

Nano- and Atom-scale Length Metrology

October 1, 2010
Author(s)
Theodore V. Vorburger, Ronald G. Dixson, Ndubuisi G. Orji, Joseph Fu, Richard A. Allen, Michael W. Cresswell, Vincent A. Hackley
Measurements of length at the nano-scale have increasing importance in manufacturing, especially in the electronics and biomedical industries. The properties of linewidth and step height are critical to the function and specification of semiconductor

MEMS Young's Modulus and Step Height Measurements with Round Robin Results

September 30, 2010
Author(s)
Janet M. Cassard, Richard A. Allen, Craig D. McGray, Jon C. Geist
This paper presents the results of a microelectromechanical systems (MEMS) Young s modulus and step height round robin experiment, completed in April 2009, which compares Young s modulus and step height measurement results at a number of laboratories. The