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Displaying 1 - 25 of 40

Layer ensemble averaging for fault tolerance in memristive neural networks

February 1, 2025
Author(s)
Osama Yousuf, Brian Hoskins, Karthick Ramu, Mitchell Fream, William Borders, Advait Madhavan, Matthew Daniels, Andrew Dienstfrey, Jabez McClelland, Martin Lueker-Boden, Gina Adam
Advancements in continual learning with artificial neural networks have been fueled in large part by scaling network dimensionalities. As this scaling continues, conventional computing systems are becoming increasingly inefficient due to the von Neumann

Measurement-driven neural-network training for integrated magnetic tunnel junction arrays

May 14, 2024
Author(s)
William Borders, Advait Madhavan, Matthew Daniels, Vasileia Georgiou, Martin Lueker-Boden, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland, Brian Hoskins
The increasing scale of neural networks needed to support more complex applications has led to an increasing requirement for area- and energy-efficient hardware. One route to meeting the budget for these applications is to circumvent the von Neumann

Advancing Measurement Science for Microelectronics: CHIPS R&D Metrology Program

February 13, 2024
Author(s)
Marla L. Dowell, Hannah Brown, Gretchen Greene, Paul D. Hale, Brian Hoskins, Sarah Hughes, Bob R. Keller, R Joseph Kline, June W. Lau, Jeff Shainline
The CHIPS and Science Act of 2022 called for NIST to "carry out a microelectronics research program to enable advances and breakthroughs....that will accelerate the underlying R&D for metrology of next-generation microelectronics and ensure the

A Fully Integrated, Automatically Generated DC-DC Converter Maintaining > 75% Efficiency From 398 K Down to 23 K Across Wide Load Ranges in 12-nm FinFET

January 1, 2024
Author(s)
Anhang Li, Jeongsup Lee, Prashansa Mukim, Brian Hoskins, Pragya Shrestha, David Wentzloff, David Blaauw, Dennis Sylvester, Mehdi Saligane
This paper presents a fully integrated recursive successive-approximation switched capacitor (RSC) DC-DC converter implemented using an automatic cell-based layout generation in 12 nm FinFET technology. A novel design methodology is demonstrated based on

Experimental demonstration of a robust training method for strongly defective neuromorphic hardware

December 11, 2023
Author(s)
William Borders, Advait Madhavan, Matthew Daniels, Vasileia Georgiou, Martin Lueker-Boden, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland, Brian Hoskins
Neural networks are increasing in scale and sophistication, catalyzing the need for efficient hardware. An inevitability when transferring neural networks to hardware is that non-idealities impact performance. Hardware-aware training, where non-idealities

Neural networks three ways: unlocking novel computing schemes using magnetic tunnel junction stochasticity

September 28, 2023
Author(s)
Matthew Daniels, William Borders, Nitin Prasad, Advait Madhavan, Sidra Gibeault, Temitayo Adeyeye, Liam Pocher, Lei Wan, Michael Tran, Jordan Katine, Daniel Lathrop, Brian Hoskins, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland
Due to their interesting physical properties, myriad operational regimes, small size, and industrial fabrication maturity, magnetic tunnel junctions are uniquely suited for unlocking novel computing schemes for in-hardware neuromorphic computing. In this

Magnetic tunnel junction-based crossbars: improving neural network performance by reducing the impact of non-idealities

July 13, 2023
Author(s)
William Borders, Nitin Prasad, Brian Hoskins, Advait Madhavan, Matthew Daniels, Vasileia Gerogiou, Tiffany Santos, Patrick Braganca, Mark Stiles, Jabez J. McClelland
Increasingly higher demand in chip area and power consumption for more sophisticated artificial neural networks has catalyzed efforts to develop architectures, circuits, and devices that perform like the human brain. However, many novel device technologies

Low-Rank Gradient Descent for Memory-Efficient Training of Deep In-Memory Arrays

May 18, 2023
Author(s)
Siyuan Huang, Brian Hoskins, Matthew Daniels, Mark Stiles, Gina C. Adam
The movement of large quantities of data during the training of a Deep Neural Network presents immense challenges for machine learning workloads. To minimize this overhead, espe- cially on the movement and calculation of gradient information, we introduce

Ultrafast ID-VG Technique for Reliable Cryogenic Device Characterization

March 21, 2023
Author(s)
Pragya Shrestha, Akin Akturk, Brian Hoskins, Advait Madhavan, Jason Campbell
An in-depth understanding of the transient operation of devices at cryogenic temperatures remains experimentally elusive. However, the impact of these transients has recently become important in efforts to develop both electronics to support quantum

Implementation of a Binary Neural Network on a Passive Array of Magnetic Tunnel Junctions

July 18, 2022
Author(s)
Jonathan Goodwill, Nitin Prasad, Brian Hoskins, Matthew Daniels, Advait Madhavan, Lei Wan, Tiffany Santos, Michael Tran, Jordan Katine, Patrick Braganca, Mark Stiles, Jabez J. McClelland
The increasing scale of neural networks and their growing application space have produced a demand for more energy and memory efficient artificial-intelligence-specific hardware. Avenues to mitigate the main issue, the von Neumann bottleneck, include in

Gradient Decomposition Methods for Training Neural Networks with Non-Ideal Synaptic Devices

November 22, 2021
Author(s)
Junyun Zhao, Siyuan Huang, Osama Yousuf, Yutong Gao, Brian Hoskins, Gina Adam
While promising for high capacity machine learning accelerators, memristor devices have non-idealities that prevent software-equivalent accuracies when used for online training. This work uses a combination of Mini-Batch Gradient Descent (MBGD) to average

Impact ionization-induced bistability in CMOS transistors at cryogenic temperatures for capacitorless memory applications

July 29, 2021
Author(s)
Alexander Zaslavsky, Curt A. Richter, Pragya Shrestha, Brian Hoskins, Son Le, Advait Madhavan, Jabez J. McClelland
Cryogenic operation of complementary metal oxide semiconductor (CMOS) silicon transistors is crucial for quantum information science, but it brings deviations from standard transistor operation. Here we report on sharp current jumps and stable hysteretic

A System for Validating Resistive Neural Network Prototypes

July 27, 2021
Author(s)
Brian Hoskins, Mitchell Fream, Matthew Daniels, Jonathan Goodwill, Advait Madhavan, Jabez J. McClelland, Osama Yousuf, Gina C. Adam, Wen Ma, Muqing Liu, Rasmus Madsen, Martin Lueker-Boden
Building prototypes of heterogeneous hardware systems based on emerging electronic, magnetic, and photonic devices is an increasingly important area of research. On the face of it, the novel implementation of these systems, especially for online learning

Room-temperature skyrmions in strain-engineered FeGe thin films

June 8, 2020
Author(s)
Sujan Budhathoki, Arjun Sapkota, Ka M. Law, Smriti Ranjit, Bhuwan Nepal, Brian Hoskins, Arashdeep S. Thind, Albina Y. Borisevich, Michelle E. Jamer, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart, Gregory M. Stephen, Don Heiman, Tim Mewes, Rohan Mishra, James C. Gallagher, Adam J. Hauser
Skyrmion electronics hold great promise for low energy consumption and stable high information density, and stabilization of Skyrmion lattice (SkX) phase at or above room temperature is greatly desired for practical use. Topological Hall Effect can be used

Radiation damage of liquid electrolyte during focused X-ray beam photoelectron spectroscopy

April 12, 2020
Author(s)
Christopher M. Arble, Hongxuan Gou, Evgheni Strelcov, Brian D. Hoskins, Patrick Zeller, Matteo Amati, Luca Gregoratti, Andrei A. Kolmakov
Ambient pressure X-ray photoelectron spectroscopy (APXPS) has become an effective tool to interrogate chemical states at surfaces relevant to real operational conditions. Herein we employ a graphene-capped microvolume array sample platform for scanning

Streaming Batch Gradient Tracking for Neural Network Training

April 3, 2020
Author(s)
Siyuan Huang, Brian D. Hoskins, Matthew W. Daniels, Mark D. Stiles, Gina C. Adam
Faster and more energy efficient hardware accelerators are critical for machine learning on very large datasets. The energy cost of performing vector-matrix multiplication and repeatedly moving neural network models in and out of memory motivates a search