Wire Bonding to Advanced Copper-Low-K Integrated Circuits, the Metal/Dielectric Stacks, and Materials Considerations

Published

November 1, 2001

Author(s)

George G. Harman, C E. Johnson

Abstract

There are three areas to consider when planning to wire bond to new chips having copper bond pads and low dielectric-constant polymers imbedded beneath them (Cu/LoK). These Are: 1/. The Top Surface Metal/Inhibitor Coating for Bondability. (a) Metal(s) (b) OSPs and other non-metal oxidation supressants. 2/. The low dielectric constant materials. (a) Mechanical properties (b) Dielectric/barriers/electrical. 3/. Under-Pad mechanical support structures. There are also various polymer/metallurgical interactions that can occur during the wire bonding interconnection process when bond pads are located over low modulus polymers (or a higher modulus if heated near its glass transition temperature, Tg, during bonding). Some of the same problems are encountered when bonding to multichip modules (MCM-d and-L), polymer buildup-layers on PCBs, PBGAs, flex circuits, etc., and they share the same understanding and solutions. However, special conditions exist for each of the above. These are discussed in detail with special emphasis on Cu/LoK structures and bondability problems.

Proceedings Title

Proc., IMAPS

Conference Dates

October 9-11, 2001

Conference Location

Baltimore, MD, USA

Conference Title

2001 IMAPS

Pub Type

Conferences

Keywords

bondability, copper, LoK, OSP, polymer, wire bonding

Citation

Harman, G. and Johnson, C. (2001), Wire Bonding to Advanced Copper-Low-K Integrated Circuits, the Metal/Dielectric Stacks, and Materials Considerations, Proc., IMAPS, Baltimore, MD, USA (Accessed July 27, 2024)