Integrated Testbeds for Advanced Metrology

Summary

As the demand for computation grows, new materials and devices are being identified with the potential to provide energy-efficient primitive operations—especially in artificial intelligence and edge computing applications. Electrical characterization of these devices is difficult using conventional approaches; to measure nanoscale devices, one needs nanoscale measurement tools. The Integrated Testbeds for Advanced Metrology program develops both general-purpose and problem-specific circuits, taped out in conventional complementary metal-oxide semiconductor (CMOS) processes, that open the possibility of high-quality electrical characterization on nanoscale systems and structures.

Description

Figure 1: (left) Design for a 20,000 device crossbar array in collaboration with University of Maryland, College Park and University of California, Santa Barbara. (right) The final wafer taped out in 180 nm technology containing the crossbar design. The wafer was extracted mid-production to allow for easy back-end-of-line integration of novel nanodevices.

Credit: NIST

Crossbar Memory Arrays

An especially prolific structure in memory architectures aimed at accelerating neural network operation is the crossbar array (Fig. 1). We produce medium-scale arrays that hold up to 20,000 nanodevices which can be characterized, read from, and written to individually or in highly parallel operations. Once packaged, these arrays can be accessed either on traditional probe stations via custom NIST-designed probe cards (Fig. 2), or by integration with our Advanced Prototyping Platform.

The low line resistances and high numbers of devices allow us to characterize statistical properties of device fabrication processes beyond what could be possible with probes in a probe station and microscopes. For instance, one can measure the parallel resistance of hundreds of devices to within X percent accuracy. The capacity for measuring thousands of devices at one time allows for statistical characterization, which is important for understanding the quality of device growth and fabrication processes. Such measurements would take weeks or even months if caried out one device at a time. The speed at which these measurements are carried out is accomplished by two mechanisms: first the crossbar structure allows for parallel addressing of many devices at once; second even performing single device measurements on the crossbar is drastically accelerated due to the experimental control provided by integration with an FPGA system, developed as part of our nano device advanced pro testing platform.

Nanotechnology Xccelerator Project

The Nanotechnology Xccelerator Project (NXP) was a collaboration between NIST, Google, Skywater, Cadence, and thirteen universities and national laboratories to produce special multiproject wafers (MPWs) with the final metal layer left off during fabrication. After chemical-mechanical polishing, these wafers have extremely smooth surfaces, ideal for nanodevice growth. Excluding the final layer from production allows researchers to grow nanodevices directly on exposed vias—that is, the devices can be grown such that they interface directly with the inner CMOS circuits, allowing for high quality device characterization and powerful prototyping capabilities.

Figure 2: Example chip designs from the NXP.

Credit: NIST

These wafers are available for academic partners, and contain a variety of useful circuits designs, outlined below. Contact nanotechnologyxccelerator [at] nist.gov (nanotechnologyxccelerator[at]nist[dot]gov) for more information.

Memory device structures
The largest memory array on the NXP wafer is an 18 kbit array for two-terminal devices that can be used for medium-scale device characterization and prototyping. The wafer also includes two 1 kbit chips that can be used for three-terminal device characterization and prototyping: one for conventional 5 V voltage sources as well as a 20 V chip that could be used for high-voltage devices such as FeRAM.

In addition, the wafer includes a reference resistor comparator (MEM-ID) tile, an endurance testing design on a 10x10 memory array, and a heterogeneous integration test vehicle for testing the contact reliability of material bonding on the chip surface.

Biosensing capabilities
The NXP wafer contains test vehicles for measuring biomembrane currents, a biocapactive sensor array, a biomanufacturing test vehicle, an ion-sensitive field effect transistor array, and a multimodal biosensor module for pH, electrochemical, and bioluminescence detection.

Magnetic device sensing and characterization
The NXP wafer contains magnetic sensors capable of operating in cryogenic temperatures, circuits for radio-frequency (RF) characterization of magnetic nanodevices, and a set of test structures for characterizing and prototyping on superparamagnetic tunnel junction devices, for applications to stochastic and probabilistic computing.

Educational tiles
In addition to designs focused on the core memory arrays, the NXP wafer also includes an analog gate array tile. This tile is geared towards providing university students with a novel capability to physically build an analog circuit design in less than 1 week. The chip consists of approximately 6000 transistors (along with resistors and capacitors) which can be electrically connected in any topology using a single metal layer. The novel routing is aided by special routing tiles distributed through the chip. The feature size (2 microns) is designed to be compatible with modern high-speed laser writers commonly found in university nanofabrication facilities.