Prototyping Platforms for Emerging Technologies

Summary

Prototyping is the critical step that links research and development to product commercialization, but the cost and expertise required to build prototypes leaves many promising technological possibilities unfulfilled. The Alternative Computing Group is developing highly flexible platforms that can be used for measurement, characterization, and prototyping of novel computing systems in the field of CMOS+X, where advanced materials uncovered by condensed matter physicists and material scientists can be utilized to provide next-generation functionality in application-specific computing contexts.

Description

Emerging technologies aim to overcome traditional memory limitations with higher density, lower power consumption, faster read/write speeds, better endurance, and lower cost [2]. Many new candidate memory elements are analog or stochastic, requiring new testing infrastructure, and the context of their use-cases in compute-in-memory or AI hardware applications necessitates benchmarks and metrics that focus on performance beyond the von Neumann architecture. Yet device-level development often occurs in small-scale research facilities or academic labs, making systems-level demonstrations challenging. Standardizing testbeds, benchmarks, and metrics could bridge the gap between research and industry, accelerating the development of next generation memory technologies.

Fundamentally, transitioning a novel memory technology from the individual device prototypes to the industrial scale requires an immense investment of resources. While a given industrial or academic research lab may have the skillsets necessary to develop the novel memory initially—such as material characterization or device fabrication—these teams lack the knowledge and capabilities to develop the technology at a practical scale. Such evaluations require significant infrastructure and specialized knowledge, including the creation of custom frameworks for rapid device measurement and a thorough understanding of statistical methods for system-level analyses that allow valid comparisons with other technologies. As a result, there is a notable gap between the innovation of novel memory technologies and their comprehensive evaluation at a system level. The Prototyping Platforms for Emerging Technologies project works to develop testbeds for prototypical and emerging memory devices and standard sets of device tests and application benchmarks for evaluating these devices.

Figure 1: The original Daffodil characterization and prototyping platform. The FPGA development board, left, hosts a PCB daughterboard, right. Within the daughterboard is a socket that hosts a packaged semiconductor chip with emerging memory technologies integrated back-end-of-line (gray-and-gold square, center-right).  

Credit: NIST

The Daffodil Board 

The Alternative Computing Group’s original vision for memory characterization and prototyping platforms arose from the need to validate and benchmark resistive neural network hardware. This platform, broadly referred to as Daffodil, is a three-part system: a field-programmable gate array (FPGA) control system hosting a soft CPU and various custom register-transfer level (RTL) codes; a mixed-signal daughterboard connecting the FPGA to a variety of signal generation and detection circuits; and a packaged silicon chip consisting of a 20,000 device memory array that could be plugged directly into the daughterboard. The CPU runs a custom, NIST-designed Linux kernel, where access to the memory array appears as a peripheral in the system’s device tree.

In order to make this platform accessible to academic researchers, NIST, in collaboration with Western Digital and George Washington University’s ADAM Lab, developed a stack of Python libraries for interfacing with the memory array. The daffodil-lib package defines an abstract interface which can be reified over either the actual hardware or over a detailed simulation model of the hardware. The availability of this simulation system is primarily to test measurement routines before applying them to memory arrays, which can often be delicate. It also provides a convenient interface for validating device models against experimental devices in a way that controls for peripheral circuit dynamics.

Figure 2: Organization of original Daffodil system. Software models (bottom right) mimic the behavior of the actual daughterboard interface to provide a safe testing environment. Custom coprocessors can be developed on the FPGA to interact directly with the chip for optimized measurement routines. 

Credit: NIST

The Daffodil system has been used successfully in collaboration with both industrial and academic groups to validate medium scale arrays of magnetic and memristive memories and prototype their use as AI hardware accelerators.

Memory Device Characterization Platform Program 

Capitalizing on the success of the original Daffodil platform, the Alternative Computing Group is currently engaged in optimizing and maturing the system to increase its accessibility to industry and academic research organizations. Funded in part by the CHIPS Metrology Program, this project aims to consolidate the FPGA and the PCB into a single hardware test vehicle.

The work of this project includes:

• increasing signal speed and fidelity
• adding flexibility and accessibility through the addition of a PCIe interface
• creating a suite of standard benchmarking and characterization routines in collaboration with the Applied Physics Division
• publishing documentation and training materials to aid in the platform’s adoption.

We also intend to develop a suite of chips beyond the 20,000-device memory array that can all be used in the new Daffodil platform for advanced measurement capabilities, dovetailing with our program on integrated testbeds.

Figure 3. Testing a fabricated semiconductor chip (center) packaged with several hundred pins that connect it to the Daffodil platform.

Credit: NIST

Finally, we expect to collaborate with academic partners to develop university lab curricula using this hardware testbed. By providing students the opportunity to work with and characterize memory arrays at a statistically relevant, near-industrial scale, we expect this program to aid in the workforce development needed to support semiconductor manufacturing, especially around memory systems and emerging technologies.