Sheet and Line Resistance of Patterned SOI Surface Film CD Reference Materials as a Function of Substrate Bias

Published

April 1, 1999

Author(s)

Richard A. Allen, Eric M. Vogel, Loren W. Linholm, Michael W. Cresswell

Abstract

Recently, NIST has been developing electrical test structures to serve as a critical dimension (CD) reference artifacts for calibrating CD metrology systems. The reference artifacts are fabricated in monocrystalline silicon-on-insulator films and are responsive to the goals of the National Technology Roadmap for Semiconductors beyond the 120 nm generation. The features on these reference artifacts are produced with lattice-plane specific etch techniques which give vertical, atomically planar sidewalls and uniform conductivity. The electrical linewidths, or electrical CDs (ECDs), of these features are determined from the sheet resistance and the resistance of the feature. This paper reports on measurements and models of how the resistance per unit length changes as a function of substrate bias providing a method to validate the calculated sheet resistance and linewidth facilitating the use of this uniquely high repeatability and low-cost metrology tool in the production of CD-reference artifacts.

Proceedings Title

Proc., IEEE International Conference on Microelectronic Test Structures

Issue

158

Conference Dates

March 15-18, 1999

Conference Location

Goteborg, 1, SW

Pub Type

Conferences

Keywords

critical dimension, linewidth, metrology, reference material, semiconductor processing, surface depletion

Citation

Allen, R. , Vogel, E. , Linholm, L. and Cresswell, M. (1999), Sheet and Line Resistance of Patterned SOI Surface Film CD Reference Materials as a Function of Substrate Bias, Proc., IEEE International Conference on Microelectronic Test Structures, Goteborg, 1, SW (Accessed July 17, 2024)