Frequently Asked Questions: CHIPS NAPMP NOFO 2

The application process consists of a mandatory concept paper and a full application. Full applications will only be accepted from applicants invited after the concept paper stage.  

This funding opportunity seeks proposals for R&D activities that will establish and accelerate domestic semiconductor advanced packaging through investments in five (5) R&D Areas: (1) Equipment, Tools, Processes, and Process Integration; (2) Power Delivery and Thermal Management; (3) Connector Technology, including Photonics and Radio Frequency (RF); (4) Chiplets Ecosystem; and (5) Co-design/Electronic Design Automation (EDA). 

Concept papers must be received no later than 11:59 p.m. Eastern Time, December 20, 2024. Following the concept review period, invited applicants will have 60 days to submit full applications. Concept papers and full applications received after the specified deadlines will not be reviewed or considered.

Eligible applicants may submit only one concept paper per R&D Area. However, applicants may submit separate concept papers on different R&D Areas

In some instances, Letters of Commitment are required. Refer to Section 4.6.1.11 of the NOFO for full Letters of Commitment requirements.  

No. Letters of interest are optional and, where included, should indicate willingness from any third party to support this proposed effort. 

Letters of interest do not contribute to the Concept Paper Narrative page limit. Letters of interest are optional and, where included, should indicate willingness from any third party to support this proposed effort.

Full applications will be accepted only from those applicants invited after concept paper evaluation. Full applications must be received at Grants.gov no later than 11:59 p.m. Eastern Time, 60 days from the date of invitation to submit.  

This NOFO identifies strict limitations on page counts for the concept paper and full application. Applicants should refer to Tables 16 (page 119) and 17 (page 136) to determine which documents and forms are included and excluded in page count limits for concept papers and full applications, respectively. 

See Section “5.6.2 Notification to Unsuccessful Applicants” of the NOFO for additional information.

There is no budget template. Applicants should follow the instructions outlined in Sections 4.5 (concept papers) and 4.6 (full applications) of the NOFO.

No. See NOFO section 4.5.1 for document submission requirements.

No. Natcast is the operator of the NSTC. This funding opportunity is through the CHIPS NAPMP.

CHIPS R&D encourages applicants to consult the CHIPS R&D Education and Workforce Development (EWD) Plan Guidebook as well as the Department of Commerce Workforce Development Strategy Principles. More information about EWD plans for this funding opportunity can be found in section 1.7.1 of the NOFO. More information about EWD plans for this funding opportunity can be found in section 1.7.1 of the NOFO.

Yes, applicants can be subrecipients on applications covering multiple R&D areas and on multiple applications within each R&D area.

CHIPS R&D anticipates making available up to approximately $1.55 billion for funding multiple awards of varying size and scope, with anticipated amounts ranging from approximately $10 million to approximately $150 million in Federal funds per award over a five year period of performance. 

Construction activities are not an allowable cost under this program. However, costs related to internal modifications of existing buildings that would be necessary to carry out the proposed research tasks may be allowed at NIST’s sole discretion. 

A non-Federal cost share over the lifetime of an award is strongly encouraged but not required. 

Cost share may include cash, services, and third-party in-kind contributions, as described at 2 C.F.R. § 200.306. Applicants may propose other types of cost share, provided that the proposed cost share is necessary and reasonable for accomplishment of the project objectives and approved by NIST. 

Yes. If an applicant wants to pursue prototyping outside of the NAPPF, they can include that information in their application. Where applicable, applicants are expected to implement their research outputs in the NAPPF once it is established.

Eligible applicants are domestic non-profit organizations; domestic accredited institutions of higher education; State, local, and Tribal governments; and domestic for-profit organizations.  

A domestic entity is one that is incorporated within the United States (including a U.S. territory) with its principal place of business in the United States (including a U.S. territory). 

Yes. CHIPS R&D strongly encourages proposals from teams that demonstrate collaboration across the innovation, manufacturing, supply chain, and customer landscape, as well as across the industry, non-profit, and academic sectors. 

To protect national security and the resiliency of supply chains, CHIPS for America funds may not be provided to a foreign entity of concern, such as an entity that is owned by, controlled by, or subject to the jurisdiction or direction of the governments of China, Russia, North Korea, or Iran. Complete definitions of foreign entity of concern and foreign country of concern are found at 15 CFR part 231.

Entities leading an application for CHIPS R&D funding must be domestic entities. Foreign organizations that are not a foreign entity of concern can participate in CHIPS R&D programs as funded subrecipients or as unfunded participants, subject to the disclosure, review, and approval processes applicable to the funding opportunity. CHIPS R&D approval processes will consider the following: 

1. That the foreign partner’s involvement is essential to advancing program objectives, such as by offering access to unique facilities, IP, or expertise that is otherwise not readily available in the United States;
2. The adequacy of any agreements and protocols between the applicant and foreign partner regarding IP protection and data protection; 
3. The partnership does not jeopardize the soundness of the project’s proposed pathway to domestic production; 
4. As applicable, the foreign partner will comply with any necessary nondisclosure agreements, security regulations, export control laws, audit requirements, and other governing statutes, regulations, and policies; 
5. The foreign partner is not based in a foreign country of concern as defined at 15 U.S.C. §4651(7) and implemented by the final rule entitled Preventing the Improper Use of CHIPS Act Funding, 88 FR 65600 (Sept. 25, 2023), codified at 15 C.F.R. §231.104; and 
6. The foreign partner agrees to be subject to a research security review by CHIPS R&D, which may include a risk assessment of IP leakage, if appropriate.

Awardees are not required to be members of the NSTC to receive funding.

No, a FFRDC may not be a lead applicant. However, Federally Funded Research and Development Centers (FFRDCs) may participate in awards as subrecipients or as contractors, to the extent allowed by law, based on the unique and specific needs of the project. See section 3.1.1 of theNOFO for more information.

Scaling out refers to increasing the number of chips assembled on the substrate and overall functional density in both two-dimensional (2D) and three-dimensional (3D) architectures.

The NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility will combine state-of-the-art manufacturing and packaging and next-generation technology development to provide NSTC members and NAPMP funded researchers with 300mm research, prototyping, and packaging capabilities. 

More information about this facility, and the other CHIPS R&D facilities, can be found here. 

Awardees are not required to be members of the NSTC to receive funding.

The NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility is expected to be operational in 2028.

More details on “wire abundance” can be found in the NOFO in section 1.6.4. Applicants may also find it useful to review the NAPMP vision paper and NOFO 2 Chiplet Webinars at chips.gov for more discussion on the meaning of the term “wire abundance.”

The NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility is expected to be operational in 2028.

Proposals within this R&D area should focus on developing: (1) advanced, flexible, extensible process technologies and integration sequences required to produce a packaged subassembly; and (2) packaging equipment to run the advanced processes and to handle the required substrates, wafers and dies, all at scaled down dimensions and designed for use at commercial scale. 

Processes and assembly methods used in conventional packaging, such as solder-based assembly and saw blade dicing. 

A good proposal delivers the entire solution, not just component technologies. The NOFO is open to a variety of proposer structures, but even large organizations may struggle to have all the resources and technologies to deliver a full solution, and thus teaming activity is often a successful strategy. 

Applications are encouraged from multi-disciplinary, multi-organization project teams that collectively demonstrate the full range of development capabilities required to achieve program objectives. Please see the CHIPS R&D Teaming List to explore opportunities. 

The NOFO targets significant advances over state of the art. Proposals must clearly show how solutions will achieve the scale-down dimensions and scale-out assembly targets required for chiplet-based adv. packaging architectures. 

IPF development will require an extensive understanding of the process technologies, integration sequence and equipment capabilities developed in the clusters. While the NOFO is open a variety of proposal structures, IPF development plans that are linked to major cluster development programs are encouraged. 

Applicants are expected to implement their research outputs in the NAPPF once established, and sign associate recipient agreements with other performers as needed.

Throughput targets are intended to drive development of production-capable tools and processes. Tool configuration is at the proposer’s discretion. 

Per the R&D Design Targets in NOFO Section 1.6.1.10, representative chiplet sizes are for cluster and process flow development. To ensure accurate and reliable handling of relevant chiplet sizes, equipment should be capable of handling both large and small chiplets. Proposals including capability for additional chiplet sizes are permitted; however, a detailed explanation on why additional sizes are needed is required in the proposal.

Per NOFO section 1.5.1.2, this R&D Area objective is to develop the processes and tools for chiplet-based packaging architectures. Development is application-agnostic, with results applicable to a range of applications.

Equipment, tools, and processes needed for packaging assembly of chiplets, including optoelectronic chips, and/or connectors (including RF and Photonics) are in scope for R&D area #1 (NOFO section 1.6.1). They are also in scope for R&D Area #3 (NOFO Section 1.6.3) as part of the development of a connector solution. 

• Thermal and power solutions that are modular, reusable, and useful for multiple applications within the chiplet ecosystem
• ·Thermal management
  • Vertical heat extraction
  • Local heat spreading
  • Embedded cooling
  • Advanced methods for active and passive cooling of 3DHI devices to reliably operate at higher power density
• Wide bandgap chiplets using 3DHI for power delivery
• Advanced models, materials, and architectures to achieve specific thermal goals such as low-resistance thermal interfaces
• On chiplet embedded structures, passives, 3D stacks, and films for power delivery and thermal management

Single application thermal and power solutions, conventional air-cooling approaches, discrete packaged devices and passives, and development of batteries are all out of scope.

There are several interdependencies between R&D Areas. Proposers are encouraged to carefully read the NOFO for details on goals and timeline for where their work best fits. The government cannot fund the same capability under multiple awards.

With proper explanation, proposals that do not meet listed targets, or those that include additional targets, will be considered. Applicants must indicate whether they will meet, exceed, or not meet the target or whether the target is not applicable for their approach.

A driver for this work is to ensure that thermal dissipation and power delivery will no longer be gating factors that limit advanced packaging. Any innovation that furthers this goal, that is not specifically stated as out of scope, will be considered

Proposers are encouraged to keep in mind the end goal of developing solutions and transferring the leading solutions to the NAPPF or other facilities for prototyping and piloting, with the best solutions made accessible to the CHIPs ecosystem. Anything required to do that should be inside the system boundary. For example, a laboratory scale chiller used to evaluate a thermal solution would be within scope. A data center scaled chiller probably would not be.

Proposers are encouraged to carefully read Section 1.8 Project Coordination of the NOFO for guidance about coordination activities to plan into a submission.

Chiplet sub-assembly to substrate connectors and connection techniques, such as:

Automated, low loss, reliable fiber attachment approaches such as high fiber count fiber array units (FAUs) that may contain polarization maintaining fibers; and Flip-chip optical connections, including evanescent coupling, between substrate waveguides and transceiver chiplets.

Traditional ball grid array (BGA) or land grid array (LGA) connectors, conventional wire bonding, and traditional free space optical components are all out of scope.

The Connectors R&D Area assumes that solutions are based on chiplets, and that all tooling and automation needed for a connector assembly will be developed under this R&D Area. It will be necessary to collaborate with other NAPMP awardees, such as for ETPI, Chiplets, and Substrates R&D Areas.

A good proposal delivers the entire solution, not just component technologies. The NOFO is open to a variety of proposer structures, but even large organizations may struggle to have all the resources and technologies to deliver a full solution, and thus teaming activity is often a successful strategy.

While we do not include specific metrics for assembly, proposals should address manufacturability and where necessary include roadmap development for integration into a full manufacturing flow.

Solutions to each Objective will need to be adaptable. The context may be informed by your system needs, but a successful solution should meet the requirements of the NOFO and be compatible with other R&D Area solutions, as adapted to specific circumstances.

As explained in the NOFO Section 1.6.3.4.2, if a project cannot meet the technical target,the applicant should carefully explain how their proposed approach nonetheless represents a significant technical advance. A successful proposal may provide a thorough rationale for what can be achieved and why the technical target is unattainable within the constraints of the program.

As referenced in NOFO Section 1.6.3.4.2, the power efficiency calculation must include all the energy needed for the full functionality and performance of the connector, e.g., lasers, modulators, power delivery, error correction, clock forwarding, and pre- and post-processing of data, including any serialization/deserialization circuitry. We do exclude the power consumption attributed to the cooling of the connector system.

 A connector solution encompasses both the transceivers, which may include chiplets, and the means of propagation, such as a physical connection. All elements should be included in the proposal, and a successful proposal may highlight the innovations therein. 

 Proposals require a figure of merit, as described in Section 1.6.3.4.2, including how that figure of merit is maximized. The s-FOM will be compared between solutions within the same objective. Thus, for example, two solutions to objective 3 (lengths up to 1km) will be compared over that length scale, even if one of the solutions may overlap with another objective. If a solution will cover more than one objective, the s-FOM will be recalculated for each objective, and its respective length scale, when comparing to other proposed solutions for that objective.
 

As noted in NOFO Section 1.6.3.3, prospective applicants may propose solutions to one or more of the objectives, so long as the application addresses the required elements of each objective.

There are no constraints, and those parameters may be optimized for a particular solution.

Traditional free space optics of a single transmitter coupled to a single fiber within an independent package are out of scope.

 The NOFO does not specify the security standards that need to be met. A meritorious proposal will identify which standards will be met during validation for the connector R&D area proposal. 

We intend the 100Tb/s to be aggregate in all directions; in other words, any combination that sums to 100Tb/s. 

The NOFO does not provide specifications for the environment of the packaged device, however proposals may specify targets according to appropriate standards for the specified application. 

RF linkages are in scope

Yes, the NOFO language in Section 1.6.3.3 of “about 10Gb/s” is intended only as an example.

Development of tooling is a component of developing the assembly process. While this activity is coordinated with the ETPI programs in Section 1.6.2, specific tooling for connectors is in scope for this RDA. 

A connector that meets at least one of the objectives is within scope.

Equipment, tools, and processes needed for packaging assembly of chiplets, including optoelectronic chips, and/or connectors (including RF and Photonics) are in scope for R&D area #1 (NOFO section 1.6.1). They are also in scope for R&D Area #3 (NOFO Section 1.6.3) as part of the development of a connector solution. 

Proposal must be focused on one of two exemplar application domains, high-performance (i.e. high-performance computing, data-center AI or similar) or low-power (i.e. biomedical, AR/VR or similar). A single proposal may not address both domains.

Chiplet designs that are extensions of conventional approaches, unmodified reuse of existing chiplets, standalone chiplet designs for any function not coupled to a chiplet ecosystem, target the development of new chiplets to integrate with existing chiplets, wire bonding for D2D interconnect, and chiplet designs based on commodity packaging are all out of scope.

This capability is needed for successful execution. In the concept paper, proposers will be expected to identify potential solutions that can provide access for project execution. There are facilities in the US that provide this capability. Please see the Teaming List . Consider teaming with ETPI groups.

While not required, teaming is encouraged.

Yes, this R&D Area encourages standards that leverage wire abundance. The intent of this R&D Area is to focus on leveraging wire abundance to drive an approach that optimizes efficiency.

Yes, this requirement is intended to drive manufacturing readiness for designed solutions. Proposers must deliver either a high-performance or low-power demonstrator. There may be additional funding available to scale successful Technology Demonstrators towards wafer scale implementations.

The Co-Design and EDA RDA includes four Objectives: 1) Design Implementation and Verification (Design); 2) Embedded Security (Security); 3) Test, Repair, Resilience, Reliability, and Fault Tolerance (Resilience): 4) Independent Integration, Verification and Validation (IV&V).

Proposals for this R&D area must address at least one of Objectives 1-3, or Objective 4

Design capabilities for purely monolithic systems, silicon tapeout or core circuit IP block development; Development of any chiplet-level application, operating system (OS), or driver software; and System architecture, neuromorphic solutions, and solutions primarily focused on chiplet-level EDA

Proposals that feature hardware or manufacturing demonstrations, proposals that are based around non-cloud computing platforms, and proposals that seek to alter or replicate rather than integrate and evaluate deliverables from other Objectives.

Proposals primarily focused on new test equipment or intra-chiplet DFT techniques; Communication standards conformance demonstrations, including bit error rate (BER) demonstrations; Fault tolerant system architectures; New information coding techniques; and Demonstrated compliance with ISO 26262 or other domain-specific functional safety standards is not required.

Software security (e.g. software-based pointer checks); System security service functionality (e.g., encryption services); Secure communications protocols; Encryption techniques including fully homomorphic; Explainable AI; Anything subject to national security classification; Developing or managing external asset management capability; and Intra-chiplet hardware security techniques (e.g., physically unclonable functions, logic locking).

Open-source tools are allowed, and are neither encouraged nor discouraged.

The PADK will be defined and delivered by Objective 4, and needs to be aware of, and even contribute to, other standards and proposed standards in the ecosystem, but will be developed to meet NAPMP needs.

Proposals can cover any combination of Objectives 1-3, but they must address all the R&D aspects of each objective covered. Proposals offering the most complete solution for each Objective will be preferentially selected.

Collaboration with other performers within the R&D Area and with other R&D Areas is critically important to the success of the program, and applicants should plan for collaboration with other teams.